1. Field of the Invention
This invention relates to a digital integrated circuit and, more particularly, to a digital integrated circuit which can perform plural functions with common circuit elements.
2. Description of the Prior Art
A digital circuit is constructed of flip-flops and combination gate circuits. In an LSI (large scale integrated circuit), the number of flip-flops and combination gate circuits disposed on the same chip becomes extremely large with an increase in circuit size. As a result, the test criteria for determining its quality becomes difficult.
Conventionally, a test of such an LSI circuit is made to determine its quality by giving a test pattern to the LSI, setting an internal state of the LSI, and comparing the output pattern of the LSI with an expected value. It is easy to set an arbitrary state, in internal logic, close to an input terminal to which the test pattern is input. However, analysis of the output of the test result is difficult. This is because, although controllability is satisfactory, observability is not good. In contrast, although it is easy to observe the output of the part close to an output terminal, the arbitrary setting of the internal logic is difficult. In other words, the observability is satisfactory but the controllability is not good.
Therefore, a scan-path test method has been proposed as a method for efficiently performing an LSI test. In the scan-path test method, a test mode is provided separately from the normal mode, as an operational mode of the LSI. The flip-flops in the LSI operate as a shift register in the test mode. Data is serially transferred to each of the flip-flops by bypassing the gate circuits so that each flip-flop can be set in an arbitrary state. Also, the output of each flip-flop is transferred by bypassing the gate circuit, in the test mode, which is connected to the output terminal. Consequently, the controllability can be improved with the enhancement of the observaility in the scan-path test method.
Since test steps can be established in this scan-path test method, automation is easy. In addition, because of the improvement of both the controllability and the observability, a fault location test to determine which part in an LSI causes a malfunction can be made with a fault detection test, to decide the quality of the LSI.
To perform the LSI test by the scan-path test method, it is necessary to constitute the flip-flops of the LSI with two-port flip-flops, which can independently operate in the normal mode and in the test mode, and which can receive two inputs in dependence on the selected mode.
As described above, in order to independently execute a plurality of modes, including the test mode and the normal mode, it is aIso necessary to provide multi-port flip-flops which can operate by the independent clocks corresponding to the respective modes.
FIG. 1 shows an example of a conventional two-port flip-flop. This two-port flip-flop is constituted by a selector 61 for selecting an input signal and selecting a clock source, depending on mode, and a D type flip-flop 62. The selector 61 is composed of AND gates 63-66 and OR gates 67 and 68.
A mode setting signal is supplied from a mode setting signal input terminal 69 to one input terminal of each of the AND gates 64 and 66. The inverted mode setting signal is given from the input termanal 69 to one input terminal of each of the AND gates 63 and 65. Data ND in the normal mode is supplied from an input terminal 70 to the other input terminal of the AND gate 63. Data TD in the test mode is supplied to the other input terminal of the AND gate 64 from an input terminal 71. A clock NCK in the normal mode is fed to the other input terminal of the AND gate 65 from a clock input terminal 72. A clock TCK in the test mode is supplied to another input terminal of the AND gate 66 from a clock input terminal 73.
The outputs of the AND gates 63 and 64 are supplied to the OR gate 67. The outputs of the AND gates 65 and 66 are supplied to the OR gate 68. The output of the OR gate 67 is supplied to the data input terminal of the D type flip-flop 62. The output of the OR gate 68 is supplied to the clock input terminal of the D type flip-flop 62. The output of the D type flip-flop 62 is output from an output terminal 74.
A low level signal is supplied to the mode setting signal input terminal 69 in the normal mode. When the low level signal is supplied to the input terminal 69, the data ND from the input terminal 70 is supplied through the AND gate 63 and the OR gate 67 to the D type flip-flop 62 and, simultaneously, the clock NCK from the clock input terminal 72 is supplied to the flip-flop 62 via the AND gate 65 and the OR gate 68.
Under the test mode, a high level signal is supplied to the input terminal 69. In response to the high level signal applied to the input terminal 69, the test data TD from the input terminal 71 is supplied to the flip-flop 62 through the AND gate 64 and the OR gate 67. The test clock TCK from the clock input terminal 73 is supplied to the flip-flop 62 through the AND gate 66 and the OR gate 68.
As described above, the conventional two-port flip-flop needs the selector 61 comprising the AND gates 63 and 66 and the OR gates 67 and 68, in addition to the flip-flop 62, resulting in an increase in circuit size. Therefore, if an integrated circuit is constituted using multi-port flip-flops such as the foregoing two-port flip-flop, in order to accomplish a plurality of functions by use of the common circuit elements, there is the problem such that the required chip area increases. In addition, since the input data is supplied to the D type flip-flops through a plurality of gates, there is also the drawback that a delay occurs, caused by these gates, and it is difficult to realize a high operating speed. Further, the electric power consumption is increased, due to the increase in number of elements, so that problems such as heat generation and the like occur.